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Ordering number : EN5606
CMOS LSI
LC75725E
1/4 to 1/11 Duty Dynamic Drive VFD Driver
Overview
The LC75725E is a 1/4 to 1/11 duty dynamic drive VFD driver. It provides 43 segment outputs and 11 digit outputs. It facilitates the construction of display systems operating under the control of a controller.
Package Dimensions
unit: mm
3159-QFP64E
[LC75725E]
Features
* Dynamic drive display technique to display four to eleven digits on the VFD. * Serial data input supports CCB* format communication with the system controller. * The dimmer level is controlled by serial data input. (The dimmer has a resolution of 10 bits.) * High generality since display data is displayed without the intervention of a decoder. * All segments can be turned off with the BLK pin. * CR oscillator circuit.
SANYO: QIP64E
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VFL DI, CL, CE, BLK OSCI S1 to S43, G1 to G11 OSCO S1 to S43 G1 to G11 Ta = 85C Conditions Ratings -0.3 to +6.5 VDD - 47 to VDD +0.3 -0.3 to +6.5 -0.3 to VDD +0.3 VDD - 47 to VDD +0.3 -0.3 to VDD +0.3 10 30 300 -40 to +85 -50 to +150 mA mW C C V V Unit
Input voltage
Output voltage
V
Output current Allowable power dissipation Operating temperature Storage temperature
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TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
3398HA (OT) No. 5606-1/13
LC75725E Allowable Operating Ranges at Ta = -40 to +85C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Symbol VDD VFL VIH1 VIH2 VIL fOSC ROSC COSC toL toH tds tdh tcp tcs tch tc VDD VFL DI, CL, CE, BLK OSCI DI, CL, CE, BLK, OSCI OSCI, OSCO OSCI, OSCO OSCI, OSCO CL CL DI, CL DI, CL CE, CL CE, CL CE, CL BLK, CE Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 3 Conditions Ratings min 4.5 VDD - 45 0.8 VDD 0.8 VDD 0 1.8 1.0 10 0.5 0.5 0.5 0.5 0.5 0.5 0.5 10 3.7 5.6 22 typ 5.0 max 5.5 VDD 5.5 VDD 0.2 VDD 4.9 22 47 V V MHz K pF s s s s s s s s V Unit
Supply voltage
Input high-level voltage Input low-level voltage Guaranteed oscillator range Recommended external resistance Recommended external capacitance Low level clock pulse width High level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time BLK switching time
Electrical Characteristics in the Allowable Operating Ranges
Parameter Symbol IIH1 IIH2 IIL VOH1 Output high-level voltage VOH2 VOH3 Output low-level voltage Output off voltage Pull-down resistors Oscillator frequency Hysteresis voltage Current drain VOL VOFF RPD fOSC VH IDD Conditions DI, CL, CE, BLK: VI = 5.5 V OSCI:VI = VDD DI, CL, CE, BLK: VI = 0 V S1 to S43: IO = 5 mA G1 to G11: IO = 20 mA OSCO: IO = 0.5 mA OSCO: IO = -0.5 mA S1 to S43, G1 to G11: VFL = VDD - 45 V, Outputs off S1 to S43, G1 to G11: VFL = VDD - 45 V, VO = VDD OSCI, OSCO: ROSC = 5.6 k, COSC = 22 pF DI, CL, CE, BLK VDD: Outputs open. Display off, fOSC = 3.7 MHz, VFL = VDD - 45 V 50 100 3.7 0.1 VDD 5 -5 VDD - 2.0 VDD - 2.0 VDD - 2.0 2.0 VDD - 44 200 V V k MHz V mA V 5 Ratings min typ max 5 A A Unit
Input high-level current Input low-level current
No. 5606-2/13
LC75725E 1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 1 Pin Assignment
Top view
No. 5606-3/13
LC75725E Block Diagram
Pin Functions
Pin VFL VDD VSS OSCI OSCO Pin No. 1, 13 60 57 59 58 Function Driver block power supply connection. (Both pins must be connected.) Logic block power supply connection. Provide a voltage between 4.5 and 5.5 V. Power supply connection. Connect to the ground. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor to these pins. Display off control input. BLK = Low (VSS) ... Display off. (S1 to S43 and G1 to G11 at VFL level.) BLK = High (VDD) ... Display on. Note that serial data can be transferred while the display is turned off. Serial data transfer inputs. These pins must be connected to the system microcontroller. CL: Synchronization clock DI: Transfer data CE: Chip enable Digit outputs. These pins are P-channel open drain outputs with pull-down resistors. Segment outputs for displaying the display data transferred by serial data input. These pins are P-channel open drain outputs with pull-down resistors. I/O -- -- -- I O Handling when unused -- -- -- GND OPEN
BLK
61
I
GND
CL DI CE G1 to G11 S1 to S43
63 64 62 2 to 12 56 to 14
I
GND
O O
OPEN OPEN
No. 5606-4/13
LC75725E Serial Data Transfer Format 1. When CL is stopped at the low level
* : don't care DD: direction data
No. 5606-5/13
LC75725E
* : don't care DD: direction data
No. 5606-6/13
LC75725E 2. When CL is stopped at the high level
* : don't care DD: direction data
No. 5606-7/13
LC75725E
* : don't care DD: direction data
Figure 2
No. 5606-8/13
LC75725E CCB address: Transfer 01110110B as shown in Figure 2. DM0 to DM9: Dimmer data This dimmer data controls the duty of the G1 to G11 digit output pins and the S1 to S43 segment output pins. It consists of 10 bits, of which DM0 is the LSB. This dimmer data sets the VFD intensity to one of 993 levels. The following table gives the relationship between the dimmer data and the dimmer level.
DM9 0 0 0 1 1 1 1 1 1 1 DM8 0 0 0 1 1 1 1 1 1 1 DM7 0 0 0 1 1 1 1 1 1 1 DM6 0 0 0 1 1 1 1 1 1 1 DM5 0 0 0 to 0 0 1 1 to 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 DM4 0 0 0 DM3 0 0 0 DM2 0 0 0 DM1 0 0 1 DM0 0 1 0 Dimmer level (Ton/Tdig) 0/1024 1/1024 2/1024 to 990/1024 991/1024 992/1024 (max) 992/1024 (max) to 992/1024 (max) 992/1024 (max) Not used
Tdig: Single-digit display time (See Figure 4.) Ton: Single-digit on time (See Figure 4.)
If distortion of the digit waveforms and segment waveforms by the VFD panel used and the wiring causes spurious glowing of the VFD panel dimly, we recommend setting the dimmer level to a smaller value. GN0 to GN3: Number of display digits data This data give the number of digits displayed by the VFD panel, a number between 4 and 11. The following table gives the relationship between this setting and the digit output pins used.
GN3 0 0 0 0 1 1 1 1 GN2 1 1 1 1 0 0 0 0 GN1 0 0 1 1 0 0 1 1 GN0 0 1 0 1 0 1 0 1 Digit output pins G1 to G4 G1 to G5 G1 to G6 G1 to G7 G1 to G8 G1 to G9 G1 to G10 G1 to G11
For example, if the VFD panel displays six digits using digit output pins G1 to G6, set GN0 to 0, GN1 to 1, GN2 to 1, and GN3 to 0. D1 to D473: Display data Dn (n=1 to 473) = 1: Display on Dn (n=1 to 473) = 0: Display off D1 to D43 . . . . . . . . . . Display data for digit output G1 D44 to D86 . . . . . . . . . Display data for digit output G2 D87 to D129 . . . . . . . . Display data for digit output G3 D130 to D172 . . . . . . . Display data for digit output G4 D173 to D215 . . . . . . . Display data for digit output G5 D216 to D258 . . . . . . . Display data for digit output G6 D259 to D301 . . . . . . . Display data for digit output G7 D302 to D344 . . . . . . . Display data for digit output G8 D345 to D387 . . . . . . . Display data for digit output G9 D388 to D430 . . . . . . . Display data for digit output G10 D431 to D473 . . . . . . . Display data for digit output G11 The number of display data bits transferred depends on the number of digits displayed. For example, if the VFD panel displays six digits, display data bits D1 to D258 are transferred. There is no need to transfer display data bits D259 to D473.
No. 5606-9/13
LC75725E Example of Serial Data Transfer * Six display digits (1/6 duty)
No. 5606-10/13
LC75725E Correspondence between Display Data (D1 to D473) and Segment Output Pins
Segment output pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 G1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 G2 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 G3 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 G4 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 G5 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 G6 D216 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 G7 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 D273 D274 D275 D276 D277 D278 D279 D280 D281 D282 D283 D284 D285 D286 D287 D288 D289 D290 D291 D292 D293 D294 D295 D296 D297 D298 D299 D300 D301 G8 D302 D303 D304 D305 D306 D307 D308 D309 D310 D311 D312 D313 D314 D315 D316 D317 D318 D319 D320 D321 D322 D323 D324 D325 D326 D327 D328 D329 D330 D331 D332 D333 D334 D335 D336 D337 D338 D339 D340 D341 D342 D343 D344 G9 D345 D346 D347 D348 D349 D350 D351 D352 D353 D354 D355 D356 D357 D358 D359 D360 D361 D362 D363 D364 D365 D366 D367 D368 D369 D370 D371 D372 D373 D374 D375 D376 D377 D378 D379 D380 D381 D382 D383 D384 D385 D386 D387 G10 D388 D389 D390 D391 D392 D393 D394 D395 D396 D397 D398 D399 D400 D401 D402 D403 D404 D405 D406 D407 D408 D409 D410 D411 D412 D413 D414 D415 D416 D417 D418 D419 D420 D421 D422 D423 D424 D425 D426 D427 D428 D429 D430 G11 D431 D432 D433 D434 D435 D436 D437 D438 D439 D440 D441 D442 D443 D444 D445 D446 D447 D448 D449 D450 D451 D452 D453 D454 D455 D456 D457 D458 D459 D460 D461 D462 D463 D464 D465 D466 D467 D468 D469 D470 D471 D472 D473
No. 5606-11/13
LC75725E BLK and the Display Control Since the LSI internal data (D1 to D473 and the control data) is undefined when power is first applied, the display is off (S1 to S43 and G1 to G11 pins = VFL level) by setting the BLK pin low at the same time as power is applied. Then, meaningless display at power on can be prevented by transfering the necessary serial data from the controller while the display is off and set the BLK pin high after the transfer completes. (See Figure 3.)
Power Supply Sequence The following sequences must be observed when the power is turned on and off. (See Figure 3.) * Power on : Logic block power supply (VDD) on Driver block power supply (VFL) on * Power off : Driver block power supply (VFL) off Logic block power supply (VDD) off
Figure 3
No. 5606-12/13
LC75725E Digit Timing Chart (11 display digits) Tframe, the frame period, is Tdig x N, where N is the number of display digits. Tdig, the single-digit display time, is 2048/fosc, where fOSC is the oscillator frequency. When the number of display digits is 11 and the oscillator frequency, fosc, is 3.7 MHz, Tdig will be about 554 s and Tframe will be about 6.09 ms.
Figure 4 Sample Application Circuit
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5606-13/13

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